Project #8578 - Verilog Coding

Please help  with th problem below:

You are to design a module that accumulates statistics on an incoming data stream consisting of two individual bytes. The I/O to the module are as follows:

input clock; \\ Clock
input reset; \\ synchronous reset - active low
input clear; \\ Clears statistics when high
(synchronous)
input [7:0] DataIn1; \\ Input Data 1
input [7:0] DataIn2; \\ Input Data 2
// all outputs are registered
output [7:0] EvenParity; \\ # of data with Even parity
output [7:0] GreyCode; \\ # of data with pattern 10101010
or 01010101
output overflow; \\ =1 if any of the counters above
overflow, stays high until clear goes high

Thus, an example of this module running might behave....
                _    _   _    _   _          _    _   _   _
clock       _| |_| |_| |_| |_| |......_| |_| |_| |_| |_
                 _
clear         | |___________

DataIn1    02 AA AA ..... 02
DataIn2    03 03 55 ..... 03
EvenParity 00 01 03 05 ..... FF 00
GreyCode  00 00 01 03 .....
Overflow    0 .....                0 1

 

Subject Computer
Due By (Pacific Time) 07/03/2013 09:00 pm
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